1. Field of the Invention
The present invention relates to a loop filter for the on-chip integration of a frequency mixer, and more particularly, to a loop filter and a phase locked loop including the same, which are capable of reducing chip area by 50% or more, while providing the same performance as the existing capacitor, by replacing a high-capacitance capacitor being a passive element with a low-capacitance capacitor and an operational amplifier in designing a third-order loop filter for a phase locked loop of a frequency mixer.
2. Description of the Related Art
Frequency mixers are widely used to generate stable frequencies for transmission/reception in the fields of mobile communications.
In such frequency mixers, a phase locked loop (PLL) including a charge pump mainly uses a third-order loop filter for the purpose of a stable phase lock.
As illustrated in FIG. 1, a typical phase locked loop includes a phase detector 110, a charge pump 120, a loop filter 130, a voltage controlled oscillator (VCO) 140, and a divider 150. The loop filter 130 is implemented with a third-order loop filter illustrated in FIG. 2. Specifically, the loop filter 130 includes a first resistor R1 and a first capacitor C1 connected in series between an output terminal of the charge pump 120 and a ground terminal, a second capacitor C2 connected in parallel to the first resistor R1 and the first capacitor C1, a third resistor R3 connected between the output terminal of the charge pump 120 and an input terminal of the voltage controlled oscillator 140, and a third capacitor C3 connected between the input terminal of the voltage controlled oscillator 140 and the ground terminal.
The first resistor R1 and the first capacitor C1 of the loop filter 130 determine a zero frequency (ωz) of the phase locked loop, and the first resistor R1 and the second capacitor C2 determine a pole frequency (ωp) of the phase locked loop.
In order for the loop filter 130 to obtain a sufficient phase margin, the capacitance of the first capacitor C1 determining the zero frequency (ωz) of the phase locked loop must be large.
For example, when a phase margin of the phase locked loop is 57 degrees; an open loop unit gain frequency (ωc) is 32 KHz; an oscillation frequency (FVCO) is 2 GHz; a reference frequency (Fref) is 25 MHz; a division ratio (N) is 80; a VCO gain (KVCO) is 50 KH; and an output current (Icp) of the charge pump is 20 μA, the first resistor R1, the first capacitor C1, and the second capacitor C2 in the loop filter of FIG. 2 are 17 kΩ, 1 nF, and 80 pF, respectively.
However, these element values of the loop filter have two problems.
First, the capacitor having a capacitance of 1 nF or more occupies a large chip area when it is integrated. When assuming that the capacitance corresponding to 1 μm2 is 1 nF, an integrated circuit area of 1 mm2 is required when 1-nF capacitance is implemented by using a metal-insulator-metal (MIM) capacitor. This may cause an increase in chip areas and chip costs.
Second, the element values of the passive elements inside the loop filter have about a 20% error rate due to variations in process and temperature when they are integrated. This may seriously degrade a phase margin of a phase locked loop.
Therefore, a loop filter is usually designed with an open chip and implemented on a printed circuit board (PCB) by using chip capacitors and chip resistors, whose absolute element values are less than 1%. However, the open chip design may increase costs of individual frequency mixer parts due to an increase in number of chip resistors, chip capacitors, and wire bondings.